JPS5912617A - 温度に比例したゲート電流を使用するスイングを減少させたラッチ回路 - Google Patents
温度に比例したゲート電流を使用するスイングを減少させたラッチ回路Info
- Publication number
- JPS5912617A JPS5912617A JP58021387A JP2138783A JPS5912617A JP S5912617 A JPS5912617 A JP S5912617A JP 58021387 A JP58021387 A JP 58021387A JP 2138783 A JP2138783 A JP 2138783A JP S5912617 A JPS5912617 A JP S5912617A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- terminal
- emitter
- coupled
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 107
- 230000001105 regulatory effect Effects 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 231100000241 scar Toxicity 0.000 claims 1
- 238000007493 shaping process Methods 0.000 claims 1
- 230000008859 change Effects 0.000 description 12
- 230000007704 transition Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 230000036039 immunity Effects 0.000 description 2
- 238000004898 kneading Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004570 mortar (masonry) Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
Landscapes
- Logic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US394487 | 1982-07-01 | ||
US06/394,487 US4540900A (en) | 1982-07-01 | 1982-07-01 | Reduced swing latch circuit utilizing gate current proportional to temperature |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5912617A true JPS5912617A (ja) | 1984-01-23 |
JPH0257733B2 JPH0257733B2 (en]) | 1990-12-05 |
Family
ID=23559160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58021387A Granted JPS5912617A (ja) | 1982-07-01 | 1983-02-10 | 温度に比例したゲート電流を使用するスイングを減少させたラッチ回路 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4540900A (en]) |
JP (1) | JPS5912617A (en]) |
DE (1) | DE3322293A1 (en]) |
FR (1) | FR2529729B1 (en]) |
GB (1) | GB2123234B (en]) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6330381A (ja) * | 1986-07-18 | 1988-02-09 | 松下電工株式会社 | 軽量セメント製品の押出し成形による製造方法 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60169216A (ja) * | 1984-02-13 | 1985-09-02 | Fujitsu Ltd | フリツプ・フロツプ回路 |
US4675553A (en) * | 1984-03-12 | 1987-06-23 | Amdahl Corporation | Sequential logic circuits implemented with inverter function logic |
US4608667A (en) * | 1984-05-18 | 1986-08-26 | International Business Machines Corporation | Dual mode logic circuit for a memory array |
DE3575059D1 (de) * | 1984-09-24 | 1990-02-01 | Siemens Ag | Und-gatter fuer ecl-schaltungen. |
US4656375A (en) * | 1985-12-16 | 1987-04-07 | Ncr Corporation | Temperature compensated CMOS to ECL translator |
JPS62222711A (ja) * | 1986-03-11 | 1987-09-30 | Fujitsu Ltd | ラツチ回路 |
JPH0787348B2 (ja) * | 1986-07-31 | 1995-09-20 | 三菱電機株式会社 | 半導体集積回路装置 |
US4736125A (en) * | 1986-08-28 | 1988-04-05 | Applied Micro Circuits Corporation | Unbuffered TTL-to-ECL translator with temperature-compensated threshold voltage obtained from a constant-current reference voltage |
US4709169A (en) * | 1986-09-02 | 1987-11-24 | International Business Machines Corporation | Logic level control for current switch emitter follower logic |
US4940905A (en) * | 1987-10-20 | 1990-07-10 | Hitachi, Ltd. | ECL flip-flop with improved x-ray resistant properties |
US4894562A (en) * | 1988-10-03 | 1990-01-16 | International Business Machines Corporation | Current switch logic circuit with controlled output signal levels |
US5079452A (en) * | 1990-06-29 | 1992-01-07 | Digital Equipment Corporation | High speed ECL latch with clock enable |
EP2599220A4 (en) * | 2010-07-27 | 2014-01-08 | Freescale Semiconductor Inc | INTERRUPT, FLIP SWITCHING AND FREQUENCY PARTS |
US10436839B2 (en) * | 2017-10-23 | 2019-10-08 | Nxp B.V. | Method for identifying a fault at a device output and system therefor |
US10782347B2 (en) | 2017-10-23 | 2020-09-22 | Nxp B.V. | Method for identifying a fault at a device output and system therefor |
US10483973B2 (en) * | 2017-12-06 | 2019-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Temperature instability-aware circuit |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3795822A (en) * | 1972-08-14 | 1974-03-05 | Hewlett Packard Co | Multiemitter coupled logic gate |
US3917959A (en) * | 1974-05-02 | 1975-11-04 | Motorola Inc | High speed counter latch circuit |
US3930172A (en) * | 1974-11-06 | 1975-12-30 | Nat Semiconductor Corp | Input supply independent circuit |
US4041326A (en) * | 1976-07-12 | 1977-08-09 | Fairchild Camera And Instrument Corporation | High speed complementary output exclusive OR/NOR circuit |
US4167727A (en) * | 1977-07-08 | 1979-09-11 | Motorola, Inc. | Logic circuits incorporating a dual function input |
US4145623A (en) * | 1977-10-04 | 1979-03-20 | Burroughs Corporation | Current mode logic compatible emitter function type logic family |
DE2821231C2 (de) * | 1978-05-16 | 1980-01-24 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Master-Slave-Flipflop in Stromschalter-Technik |
US4276488A (en) * | 1978-11-13 | 1981-06-30 | Hughes Aircraft Company | Multi-master single-slave ECL flip-flop |
JPS5631137A (en) * | 1979-08-22 | 1981-03-28 | Fujitsu Ltd | Decoder circuit |
JPS56156026A (en) * | 1980-05-02 | 1981-12-02 | Hitachi Ltd | Composite logical circuit |
US4408134A (en) * | 1981-01-19 | 1983-10-04 | Advanced Micro Devices, Inc. | Unitary exclusive or-and logic circuit |
-
1982
- 1982-07-01 US US06/394,487 patent/US4540900A/en not_active Expired - Fee Related
-
1983
- 1983-02-10 JP JP58021387A patent/JPS5912617A/ja active Granted
- 1983-03-25 FR FR8304963A patent/FR2529729B1/fr not_active Expired
- 1983-06-21 DE DE19833322293 patent/DE3322293A1/de not_active Withdrawn
- 1983-07-01 GB GB08317878A patent/GB2123234B/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6330381A (ja) * | 1986-07-18 | 1988-02-09 | 松下電工株式会社 | 軽量セメント製品の押出し成形による製造方法 |
Also Published As
Publication number | Publication date |
---|---|
DE3322293A1 (de) | 1984-01-05 |
JPH0257733B2 (en]) | 1990-12-05 |
US4540900A (en) | 1985-09-10 |
FR2529729B1 (fr) | 1986-09-12 |
GB2123234B (en) | 1986-01-08 |
GB8317878D0 (en) | 1983-08-03 |
FR2529729A1 (fr) | 1984-01-06 |
GB2123234A (en) | 1984-01-25 |
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